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AN10145 bi-directional low voltage translators gtl2000, gtl2002, gtl2010 supersedes data of 2002 dec 16 alma anderson senior design engineer jean-marc irazabal technical marketing manager steve blozis international product manager specialty logic product line interface products business line 2004 aug 11 integrated circuits abstract philips semiconductors gunning transceiver logic translator voltage clamp (gtl-tvc) bi-directional low voltage translators are used in bi-directional signaling voltage level translation applications. voltage translation can be from any voltage between 1.0 v to 5.0 v to any voltage between 1.0 v to 5.0 v without need for directional control. device operation, resistor sizing and typical applications are discussed in this application note. s ref s 1 s 22 d ref d 1 d 22 g ref
2 table of contents table of co ntents .............................................................................................................. .....................................2 overview ....................................................................................................................... ................................................3 d escription ............................................................................................................................... ......................................3 a pplications ............................................................................................................................... ....................................3 f eatures ............................................................................................................................... ..........................................5 o perating c haracteristics ............................................................................................................................... ..........6 d evice p inout ............................................................................................................................... ..................................6 o rdering i nformation ............................................................................................................................... ...................7 d ata s heets and ibis m odels ............................................................................................................................... ......7 technical information .......................................................................................................... .............................7 b lock d iagram ............................................................................................................................... ...............................7 c alculating p ull -u p r esistor v alues ...................................................................................................................13 applications................................................................................................................... ...........................................14 v oltage l evel t ranslation ............................................................................................................................... ......14 frequently aske d questions ..................................................................................................... ....................15 d evice ............................................................................................................................... .............................................15 c onnecting the device to the right voltages / components .................................................................................16 a pplications ............................................................................................................................... ..................................17 additional information ......................................................................................................... ..........................23
3 overview description within the semiconductor world, there are many i/o standards that have different voltage level requirements for the input voltage (v ih or v il ) and output voltage (v oh or v ol ) typically based on the device operating voltage. these voltage levels define how the device communicates with other devices and the voltage levels are expressed as a bus standard. a few of these bus standards include 5 v cmos, 5 v ttl, 3.3 v lvttl, 2.5 v ag p graphics port an d 1.5 v gtl+ host bus. providing a migration path is important in all industry segments because system co mponents used in new designs must communicate with components using the existing bus infra structure even if they are operating at higher voltage levels. since new devices are designed and produced with advanced sub-micron semiconductor process technologies, there has to be an easy way to prevent damage to the new device and translate voltage switching levels of the higher voltage legacy device. the philips semiconductors gunning transceiver logic transl ator voltage clamp (gtl-tvc) family of bi-directional low voltage translators is designed in a bicmos process for protecting the sensitive i/os on new advanced sub micron components. the gtl-tvc devices protec t these new devices from the over voltage and esd conditions applied by the older, legacy devices and translate the v ih and v oh switching levels. the information presented in this application note describes the i/o-protection applications and voltage transl ations of the gtl-tvc family and will enable the design engineer to successfully interface devi ces with different i/o voltage levels. applications voltage level shifting the gtl-tvc devices can be used to interface between devi ces i/os operating at different voltage levels. since the gtl-tvc device is open drain on both sides, pull up resistor s may be needed depending on the i/o interface type (totem pole or open drain) and the translation direction (high to low, low to high, or bi-directional). the gtl-tvc devices allow translations between any voltages from 1.0 v to 5.0 v as long as the voltage difference between the gate and source voltages is maintained at about 1 v. the recommended circuit in figure 1 connects the gate (gref) and reference drain (dref) together through a 200 k ? resistor to a voltage, which should be at least 1.5 v above the reference source (sref) level . this circuit biases the gate to a threshold above the reference source voltage and compensates for part-to-part threshold variations. since the ga te threshold voltage can vary between 0.6 v and 1 v, if the gref to sref voltage is less than 1 v, the low voltage side high level may be degraded below the sref voltage because it can only pull up to a th reshold below the gref voltage. figure 1. typical two-bit bi-directional application 1. bi-directional translation for bi-directional translation, the drivers on both sides of the gtl-tvc device must be open drain outputs or at least they must be controlled in such a way that contention between a high level on an output driver on one side and a low level on an output driver on the other side is prevented. the easiest solution is to use open drain devices (the standard gtl and i 2 c/smbus outputs are open drain outputs). when using open drain devices, it is necessary to use pull up resistors, and they must be sized so as not to overload the output drivers nor exceed the 15 ma r ecommended current for use of a gtl-tvc device in a translation application. if the device is used for i 2 c bus translation, the resistors must be sized to provide less than 3 ma of current (i 2 c devices are specified to drive 3 ma max at 0.4 v). gnd s ref gref dref s1 s2 d2 d1 gtl200 chipset i/o cpu i/o 1.8 v 1.5 v 1.2 v 1.0 v v cor v d 5 v 200 k ?
4 when the gtl-tvc device is used as described in figure 1, it is not necessary to have pull up resistors on the lower voltage side because the gtl-tvc device will pass up to the reference source voltage. with a 200 k ? resistor connected to the reference drain (dref) and the reference gate (gref) and pulled up to a supply voltage that is at least 1.5 v higher than the reference source (sref) level , about 2.5 a will pass to the lower voltage side at the reference source voltage value. if the low voltage side is known to be leaky (more than the 2.5 a described above), it is necessary to include a pull up resistor on the low voltage side as well as the high voltage side to provide the required current value. 2. down translation when doing down translation, since there is no driver on the lower voltage side, the higher voltage driver may be either totem pole without any pull up resistor or open drain with a pull up resistor, and no resistor pull up is needed on the low voltage side unless it has excessive leakage (more than the 2.5 a described in the paragraph above). 3. up translation a pull up resistor is always required on the higher voltage side to get the full high level, since the gtl-tvc device will only pass the reference source voltage as a high when doing a up translation. a full cmos driver or an open drain driver with or without a pull up resistor on the low voltage side may be used. the resistor values must be chosen so as not to overload the pull down driver nor the 15 ma limit of the gtl-tvc devices. 4. multiple voltage bi-directional translation the channel pass transistors are constructed such that the gate of the re ference transistor (gref) pin is used to limit the maximum high voltage that will be passed by the device. this allows the us e of different bus voltages on each source to drain cha nnel so that for example, a 1.5 v device can communicate with 2.5 v, 3.3 v or 5 v devices without any additional protection. figure 2 shows how the gtl2010 can be used in a bi-directional i 2 c application where two asic?s i 2 c ports (left side) operating at 1.5 v can interface to higher voltage devices (right side) operating at 3.3v and 5.0 v. - one of the asic ports (mddc on s1 & s2) only needs to interface with 5 v i 2 c devices. - the other asic port (mi2c on s3 & s4 and s5 & s6) needs to interface with both 3.3 v smbus and 5.0 v i 2 c devices. since the voltage difference between the low voltage (1.5v, left side) and the voltage on the resistor for the gref (gate pull-up) is higher than 1.5v (5.0v in the figure), pull up resistors on the low voltage side (1.5v) are optional. note: pull up resistors on the low voltage side are required if: - te difference between the external voltage applied on the resistor for the gate reference (gref) and the voltage on the low side is lower than 1.5v - the device in the low voltage side has a leakage current value higher than 2.5 a figure 2. bi-directional multiple voltage i 2 c application
5 cross-bar technology (cbt) like behavior the large nmos pass transistors used in the gtl-tvc devices are very similar to the larg e nmos pass transistors used in cbt devices. however unlike the cbt devices that use internal drivers to control the gate of the nmos pass transistor, the gate pin of the gtl-tvc devices is directly co nnected to the gate of each transistor. in principle the gtl-tvc devices can be used like cbt devices except that the gate input capacitance is much larger than a normal cbt device. when using the gtl-tvc devices as cbt devices, the gate pin (gref) is driven by external logic to the power supply, to enable it, or to ground to disable it, and the sref and dref pins can be used as an additional channel as shown in figure 3. figure 3. cross bar technology like application note: if a 5 v to 3.3 v translation is wanted, best results are achieved using the bias circuit of the gtl-tvc with the sref at 3.3 v. additionally, when used as a cbt function with the gate at v dd and the input at v dd, the maximum pass voltage will be ~ v dd ? 1 v because the output is shifted down by a threshold compared to the gate voltage. features the gtl-tvc family has several features that benefit a system designer when designing an interface between devices with different i/o voltage levels. device construction ? the gtl-tvc devices are of a very simple design. the only required connections are gnd, gate of the reference transistor (gref), drain of the refere nce transistor (dref) and sour ce of the reference transistor (sref) and then any of the dn/sn i/o pairs needed for voltage level translations. ? any transistor dn or sn i/o pair can be used as the source or drain of the reference transistor (sref or dref). this makes it easier to route signals to and from the device. ? all the transistors are on one die, which is manufactured with very tight process control. this provides a very low spread of v o relative to sref or dref. ? it is easy to change the sref voltage allowing the system designer an easy migration path to even lower voltages (e.g. 1.5 v or 1.2 v). ? dn /sn i/o pairs are matched on either side of the devices (e.g., flow through pinout) which offers easy trace routing. no active control logic ? as shown in figure 4, the gtl-tvc is a passive device and there is no active control logic. this means there is no supply power (v dd ) required for device operation. figure 4. gtl20xx logic diagram gnd sref gref dref s1 s2 d2 d1 gtl2002 chipset i/o chip set v dd v dd 5 v control
6 wide range of bit widths and packages ? the gtl-tvc devices are offered in a wide range of bit widths and packages as shown in table 1. they are available in 2, 10 or 22 bit widths and package sizes ranging from the so and tssop packages to the small hvqfn and vssop packages. this allows the designer the maximum flexibility in picking the bit width and package that is best suited for them, should the concern be easy soldering or small form factor or wider bit width. pin count so ssop tssop vssop hvqfn gtl2000 22 48 dl dgg gtl2002 2 8 d dp dc gtl2010 10 24 pw bs # of i/o pairs device name packages table 1. gtl20xx selection table operating characteristics ? 1.0 v to 5.0 v voltage translation range ? 5.5 v tolerant i/o ports ? -40 oc to 85 oc operating temperature range ? esd protection exceeds: ? 2000 v hbm per jesd22-a114 ? 200 v mm per jesd22-a115 ? 1000 v cdm per jesd22-c101 ? latch-up is not possible because there is no v dd pin. ? manufactured in a high volume bicmos process for robust esd performance . device pinout figure 5. gtl20xx so, ssop, tssop, vssop and hvqfn pin outs gtl2000 gtl2002 gtl2010 so and tssop vssop tssop gtl2002 gtl2010 hvqfn
7 all the devices operate exactly the same and vary only on the number of i/o available. any matched set of sn and dn pins can be used as sref and dref (e.g., pin 12 and 13 on the gtl2010 can be used for sref and dref instead of pins 2 and 23 which revert to s10 and d10). ordering information table 2. gtl20xx ordering information data sheets and ibis models data sheets and ibis models can be downloaded from www.philipslogic.com technical information block diagram gtl-tvc voltage-limiting application in voltage-limiting applications, the common gref input must be connected to one side (sn or dn) of any of the transistors (see figure 6). this connec tion determines the dref input of the reference transistor. the dref and gref inputs are connected together through a pull up resistor (typically 200 k ? ) to the v dd supply. a filter capacitor (typically 0.1 f) on dref is recommended. associated with the 200 k ? resistor, the rc time constant is equal to 20 ms. the larger the capacitor, the less the gate node will move, the slower it will rise on power up. the opposite side of the reference transistor is used as th e reference voltage sref connection. the sref input should be less than v dd ? 1.5 v to insure that the reference transistor is prop erly biased into conduction. if the sref is set to less than 1.5 v below vdd, the maximum pass voltage may be less than the sref voltage b ecause the threshold voltage (the minimum gate to source voltage necessary for conduction) may be limiting the pass voltage rather than the sref voltage. the gate to source threshold voltage will vary from part to part but will not vary within a package. the reference transistor regulates the gate voltage (gref ) of all the pass transistors in the p ackage when properly biased, as described above. package container gtl2000 gtl2002 gtl2010 tube gtl2002d - t & r gtl2002d-t - tube gtl2000dl - - t & r gtl2000dl-t - - tube gtl2000dgg - gtl2010pw t & r gtl2000dgg-t gtl2002dp-t gtl2010pw-t vssop t & r - gtl2002dc-t hvqfn t & r - - gtl2010bs-t tssop ssop so gnd sref gref dref s1 s2 d2 d1 gtl2002 device cpu 1.8 v 1.5 v 1.2 v 1.0 v v core v dd 5 v 200 k ?
8 figure 6 ? gtl-tvc typica l application circuit propagation delay propagation delay for the gtl-tvc devices is problematic to define because, like the cbt functions, it is very small across the transistor. the rise time is dominated by the rc time constant of the node, and the fall time is dominated by the pull down driver, the total capacitance and the pull up resistor. the propagation delay is normally measured from ? the swing on the lower voltage side to ? the swing on the higher voltage side or vice versa. for a 0 v to 3 v transition on the input with a 1 ns edge rate to a 0 v to 3 v output, the measurement points on both sides would be 1.5 v and the propagation delay would be less than 1 ns. however, for a gtl+ to 5 v translation, where the pull up on the 5 v side is 2.2 k ? and the total capacitance is 100 pf, the rising edge propagation would be measured from the 1 v point on the gtl+ side to 2.5 v on the 5 v side and would measure about 95 ns because of the rc time constant. gtl-tvc electrical characteristics the typical electrical characteristics of the gtl-tvc nmos transistors as meas ured over temperature using the test configuration shown in figure 7 are included in figures 8 to 13. figure 7. gtl-tvc test set up -2.20e-02 -2.00e-02 -1.80e-02 -1.60e-02 -1.40e-02 -1.20e-02 -1.00e-02 -8.00e-03 -6.00e-03 -4.00e-03 -2.00e-03 0.00e+00 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 vsn (v) vsref = 1 v isn (a) 25 deg c 85 deg c -40 deg c vddref = 3.3v vddpass = 3.3v rdn = 150 ohms rdref = 200k gnd sref gref dref s1 s2 d2 d1 gtl2002 1.0 v 1.5 v 2.0 v 2.5 v vsn vdn vsref vddref vddpass rdref rdn
9 figure 8. v ? i electrical chacteristics at v sref = 1.0 volt as can be seen in figure 8, the current is controlled by the 150 ? resistor on the drain (rdn) until the source voltage is within about 0.5 volts of the sref volta ge where the pass transistor resistance increases rapidly to the point that the current through the pass transistor is just a few a. this occurs as the source (sn) voltage reaches the sref voltage. in any system, or logic level definition, there is a maximum low level input voltage (vil) specified for the device. when a gtl-tvc device is used, the series combination of the driver and gtl-tvc device must not exceed the maximum vil allowed for the logic family. normally the allowed low le vel voltage is divided between the driver and the gtl-tvc device. if the driver is weak or the allowed low level voltage is small, it would be necessary to operate at a lower current than 15 ma. for example, if the gtl-tvc device is used as a translator for an i 2 c bus, the current would be limited to 3 ma. on the other hand, if the driver is very strong and/or the allowed low level is large, it may be possible to operate the gtl-tvc device at currents higher than 15 ma, but in this cas e, it must be remembered that the voltage drop across the device will be greater than the 0.175 v maximun specified in the electrical characteristics of the data sheet. -2.2e-02 -2.0e-02 -1.8e-02 -1.6e-02 -1.4e-02 -1.2e-02 -1.0e-02 -8.0e-03 -6.0e-03 -4.0e-03 -2.0e-03 0.0e+00 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 vsn (v) vsref = 1.5v isn (a) 25 deg c 85 deg c -40 deg c vddref = 3.3v vddpass = 3.3v rdn = 150 ohms rdref = 200k figure 9. v-i electrical characteristics at v sref = 1.5 volt -2.2e-02 -2.0e-02 -1.8e-02 -1.6e-02 -1.4e-02 -1.2e-02 -1.0e-02 -8.0e-03 -6.0e-03 -4.0e-03 -2.0e-03 0.0e+00 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 vsn (v) vsref = 2v isn (a) 25 deg c 85 deg c -40 deg c vddref = 3.3v vddpass = 3.3v rdn = 150 ohms rdref = 200k figure 10. v-i electrical characteristics at v sref = 2.0 volt
10 figures 9 and 10 show the sref at 1.5 v and 2.0 v respectively. the same behavior is observed where the current shuts off quickly as the source voltage gets within about 0.5 v of the sref voltage. -2.2e-02 -2.0e-02 -1.8e-02 -1.6e-02 -1.4e-02 -1.2e-02 -1.0e-02 -8.0e-03 -6.0e-03 -4.0e-03 -2.0e-03 0.0e+00 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 vsn (v) vsref = 2.5v isn (a) 25 deg c 85 deg c -40 deg c vddref = 3.3v vddpass = 3.3v rdn = 150 ohms rdref = 200k figure 11. v-i electrical characteristics at v sref = 2.5 volt and v ddref = 3.3 volt -2.2e-02 -2.0e-02 -1.8e-02 -1.6e-02 -1.4e-02 -1.2e-02 -1.0e-02 -8.0e-03 -6.0e-03 -4.0e-03 -2.0e-03 0.0e+00 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 vsn (v) vsref = 2.5v isn (a) 25 deg c 85 deg c -40 deg c vddref = 4.0v vddpass = 3.3v rdn = 150 ohms rdref = 200k figure 12. v-i electrical characteristics at v sref = 2.5 volt and v ddref = 4.0 volt
11 -2.2e-02 -2.0e-02 -1.8e-02 -1.6e-02 -1.4e-02 -1.2e-02 -1.0e-02 -8.0e-03 -6.0e-03 -4.0e-03 -2.0e-03 0.0e+00 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 vsn (v) vsref = 2.5v isn (a) 25 deg c 85 deg c -40 deg c vddref = 5.0v vddpass = 3.3v rdn = 150 ohms rdref = 200k figure 13. v-i electrical characteristics at v sref = 2.5 volt and v ddref = 5.0 volt figures 11, 12 and 13 show the sref at 2.5 v with v ddref voltages of 3.3 v, 4.0 v, and 5.0 v respectively. note that when v ddref is 3.3 v, with only 0.8 v between v ddref and the sref voltage, the cold temperature curve turns off before the source voltage reaches the sref voltage. with v ddref voltages of 4.0 v and 5.0 v, the behavior returns to normal where the turn off point is the sref voltage, independent of temperature. the same pass transistor at hot temperatures has a higher on resistance so it starts to shut off sooner as the so urce voltage approaches the sref voltage. cbt like electrical characteristics cbt like characteristics are tested using a setup as shown in figure 14 . figure 14 ? cbt like test set up figure 15 shows typical pass transistor on resistance (r on ) as a function of source voltage with the gate at 5 v and i source = 64 ma, figure 16 shows r on with i source = 15 ma. as can be clearly seen in these figures, the r on changes only slightly as long as the source voltage is less than the gate to source voltage necessary to conduct an idsat equal to the current source curren t (64 ma for figure 15 and 15 ma for figure 16). the r on increases rapidly as the transistor is unable to conduct the high current. cbt functions are generally used with dynamic currents rather than static currents. m
12 figure 15 shows that a driver capable of first reflected wa ve switching can propagate its transition through the gtl-tvc device as a first reflected wave because, at 64 ma, the resistance is still low (~ 8 ? at 2.5 v) and only 50 ma is required to impose a 2.5 v transition into a 50 ? line (the voltage doubles at the end to 5 v). caution: it may be necessary to include a resistor in series with th e driver if its pull up is stronger than a first reflected wave driver, to prevent over shoot and ringing in an unterminated transmission line. 0 5 10 15 20 0 0.5 1 1.5 2 2.5 3 3.5 vsn (v) pass gate resistance (ohms) vgref = 5v iddpass = 64ma figure 15. electrical characteristics as a c bt like function, resista nce ? source voltage with the gate at 5.0 v and 64 ma pass current. 0 5 10 15 20 0 0.5 1 1.5 2 2.5 3 3.5 vsn (v) pass gate resistance (ohms) vgref = 5v iddpass = 15ma figure 16. electrical characteristics as a c bt like function, resista nce ? source voltage with the gate at 5.0 v and 15 ma pass current.
13 calculating pull-up resistor values the pull-up resistor value needs to limit the current through the pass transistor when it is in the "on" state to about 15 ma. this will guarantee a pass voltage of 260 to 350 mv. if th e current through the pass transistor is higher than 15 ma, the pass voltage will also be higher in the "on" state. to set the current through each pass transistor at 15 ma, calculate the pull-up resistor value as follows: table 3 below summarizes resistor values for various refere nce voltages and currents at 15 ma and also at 10 ma and 3 ma. the resistor value shown in the highlighted box or a larger value should be used to ensure that the pass voltage of the transistor would be 350 mv or less. the external driver must be able to sink the total current from the resistors on both sides of the gtl-tvc device at 0.175 v, although the 15 ma only applies to current flowing through the gtl- tvc device. pull up resistor value (ohms) 15 ma 10 ma 3 ma voltage nominal + 10 % nominal + 10 % nominal + 10 % 5.0 v 310 341 465 512 1550 1705 3.3 v 197 217 295 325 983 1082 2.5 v 143 158 215 237 717 788 1.8 v 97 106 145 160 483 532 1.5 v 77 85 115 127 383 422 1.2 v 57 63 85 94 283 312 1) calculated for vol = 0.35 v 2) assumes output driver vol = 0.175 v at stated current. 3) + 10 % to compensate for v dd range and resistor tolerance. table 3. pull up resistor values alternate sources the texas instruments tvc devices operate the same as the philips semiconductors gtl-tvc devices but have different names for the connections as shown in table 4. the data sheet specifications are marginally different. the texas instruments tvc devices are cmos construction. philips semiconductors gtl-tvc texas instruments tvc gref gate dref vbias sref vref table 4. device pin name comparison resistor value (in ?
14 applications voltage level translation figure 17 shows an application similar to the one shown in figure 2 but with only one asic i 2 c port that has to interface with both the 3.3 v and 5 v i 2 c devices. since the voltage difference between the low voltage (1.5v, left side) and the voltage on the resistor for the gref (gate pull-up) is higher than 1.5v, the resistors r30 and r25 are not required unless the devices on mi2c_clk are leaky. note: pull up resistors on the low voltage side are requi red if the difference between the voltage applied on the gate reference (gref) pull up resistor and the low side voltage is lower than 1.5 v. figure 17. example of 1.5 v i 2 c bus to both 3.3v smbus and 5.0 v i 2 c bus note: figure 2 and figure 17 are from the intel reference design. resistor sizing wo rks fine but is not in accordance with the recommendations in this application note.
15 frequently asked questions device 1. question: the gtl-tvc schematic makes these parts look like an array of nmos transistors? answer: yes, the gtl 2000, 2010 and 2002 are arrays of nmos transistors with a common gate. these parts could be used as one large nmos transistor by wiring all the sources together and all the drains together. however, they were designed as level shifters /clamps where the inherent matching is used by making one transistor a reference and the remaining transistors as level shifters/clamps. no t shown in the schematic are the esd protection devices between each pin and ground. 2. question: can any transistor in the array be used as the reference transistor? answer: yes, any transistor can be used as long as its dn pin is connected to th e gref pin and its associated sn is used as the sref. however, the dref pin is probably the eas iest to use because of its close proximity to the gref pin. 3. question: are the sn and dn pins interchangeable? answer: yes, the sn and dn labels are merely for convenience in thinking about the devices. a sn pin could be used as a drain and the corresponding dn pin used as a source. the n indicates a number, which identifies a transistor. thus, s1 and d1 correspond to transistor 1. 4. question: are both the sn and dn ports 5-v i/o tolerant? answer: yes, both the ports are 5.5 v tolerant, and the gref is also 5.5 v tolerant. 5. question: do the gtl-tvc devices isolate the capacitance in the line? answer: no, the devices don't have this capability since the device is basically an array of nmos transistors. 6. question: what will be the typical propagation delay for gtl2000 device family? answer: the gtl2000 family of devices have th e propagation delay associated with a 5 ? wire for much of the swing. thus with a 50 pf load and a low resistance driver driving the transition and measuring both sides at the same voltage level i.e. 1.5 v, the delay is about 0.25 ns. if the delay wanted is from one side gtl+ where the measurement point is 1 v to cmos at 5 v in the other side, with a 2.5 v measurement voltage, then the delay is not the 0.25 ns of the gtl2000 family part. it is rather primarily the delay of the system, that is the rc time constant of the pull-up and the line capacitance, which determine the rise time between 1 v and 2.5 v. the fall time is not affected as much because the driver's effective resistance is very low compared to the pull-up so the 2.5 v to 1 v transition is much faster than the rising transition. fo r a 3 v to 5 v level translation, the measurement point difference is much less so the propagation delay is shorter. if the 5 v part is ttl input then the measurement points are the same. 7. question: i am using a 3.3 v fpga with a gtl device on some pins. the gtl device does the level conversion, either down to 1.8v or up to 5v. the pins from the g tl device go to a connector. there is a possibility that a human being touches it and there a esd can occur. will gtl prevent the fpga from esd? i think that the gtl device is esd protected, am i right? answer: the gtl2000/10/02 devices all have esd protection > 2kv hbm and they should absorb most of the energy from an esd event. the gtl part on the connector will absorb the primary esd energy but we cannot guarantee that this will always protect the fpga. very little of the esd energy shou ld reach the fpga however. 8. question: due to the requirement of the voltage for the 200 k ? pull-up at both the gref and dref pins that has to be at least 1.5v more than the sref voltage (1.8v in this case), the voltage at the 200 k ? resistor need to be at least 3.3v. the design does not have such voltage provided other than 1.8v and 3.0v. can the gtl2010 be used? answer: the device will work with 1.2v differential but the actual voltage seen on the lower side may not be what sref sets. example would be one side at 5v and the other at 3v; you will always seen 5v and 3v. if one side is at 5v and the other at3.8v, then you will always seen 5v bu t may see > 3.8v on the other side depending on current flow. the higher voltage may not matter much unless the device in not tolerant to the higher voltage. you could also adjust the sref to the low side of the band so that the overshoot doesn't over stress the device. the problem is not that the 3.8 v side would be above 3.8 v but rather that it might only get as high as 3.5 v and that the exact value will vary from part to part and would be between 3.5 v an d 3.8 v. or in the specific case the 1.8 v side high may
16 only pull up to 1.5 v when biased with the 3 v supply. if the 1.5 v level is not high enough a high value pull-up resistor could be used to the 1.8 v supply to make certain that it gets to 1.8 v. connecting the device to the right voltages/components 1. question: in the recommended operating conditions table of the data sheet, the typical dref is 3.3 v. should dref be equal to or greater than sref on the reference transistor? answer: the sref and dref can be equal, however, for best results the dref should be connected through a 200 k ? resistor to a power supply level that is at least 1.5 v above sref. if the sref is less than 1 v below the dref, the maximum pass voltage may be limited to a voltage below sref by the threshold of the transistor (e.g. dref = 2.5 v and sref = 1.8 v). when the sref and dref are equal, the threshold of the transistor determines the maximum pass voltage. although the threshold variation within a package is small, the part-to-part variation can be larger. if the part-to-part threshold va riation is acceptable, then the gate (gref) could be tied directly to the power supply and the reference transistor used as one more pass transistor. 2. question: you said "you can use sref to clamp the sn port at 1.5 v so you can feed in the 3.3 v signal on the dn port side and clamp it at 1.5 v without having to use any pull up resistors on the lower voltage side, but going from 1.5 v to the 3.3 v you have to use pull up resistors on the 3.3 v dn port side". my understanding is that going from a higher voltage (3.3 v pci) to a lower voltage (1.5v agp) doesn't need to use any pull-up resistors unless the logic used is based in pull-up resistors (like gtl). so in our case (push-pull logic) we don't need pull-ups on the agp side. am i right? answer: if it is a uni-directional signal going from the 3.3 v pci side (push-pull) to the 1.5 v agp side (which is push pull logic so it doesn't need pull up resistors but operates in input mode only) then you don't need pull up resistors on the 3.3 v or 1.5v side except for the dref pin which sets the reference voltage. 3. question: we use only 3 bits on the gtl2010. seven of the bits are no connect (dn and sn is open). is this ok or should they be tied to gref? answer: there are several acceptable ways of dealing with un used data paths and treating them as no connects is probably the easiest. it is recommended that pads be included on the circuit board for the unused pins so that after soldering the part will be firmly attached. alternatively, the unused dn and sn pins can be connected together and tied to gnd. it is not recommended connecting unused paths to gref. 4. question: i use three gtl2000 devices for translating 66 signals from 3.3 v to 1.8 v. can the 200 k ? resistor be shared by all three gtl2000 gref and dref pins or do i need three 200 k ? resistors? what is the recommended value for the capacitor next to the 200 k ? resistor? answer: it would be best to use 3 different resistors, because different packages may not have identical characteristics and separate resistors / biasing allows the circuit to compensate for th ese differences. sharing one resistor would not work well. if the characteristics matched perfectly they would be biased with an effective 600 k ? resistor and if not perfectly matched one would be biased correctly and the other two would have too low of a gate voltage. for the capacitor, we usually recommend a 0.1 f value. note that the capacitor st abilizes the gate node but also slows its power up: with a 200 k ? resistor, it will take on the order of 100 ms to get to the correct clamp level with a 0.1 f capacitor. since the gate node has over 100 pf capacita nce the capacitor needs to be in at least the nf range to do anything. if you do not have any speed constraint at power up, then 0.1 f would be safe enough. 5. question: is it possible to use a gtl2010 to perform bi-directional voltage translation between a 1.8v device and a 3.0v device b using the 3.0v device b supply for the 200 k ? pull-up at both the gref and dref pins of gtl2010? as i understand from the gtl2010 datasheet, the pull-up supply has to be at least 1.5v more than the sref voltage (1.8v in this case)). how should i connect the different pins of the gtl2010? answer: tie the 1.8 v signal to s side. and connect the 3.0 v signal to d side. the pull-up resistor is dependant on the driving current and signal level. for a 3.0 v signal and a 15 ma driving current, the pull-up resistor value is 177 ? (normal) to 195 ? (max) as indicated in page 6 of the gtl2010 data sheet. 6. question: i am experiencing a problem with the gtl2000 when i reference the sref input to the voltage supply of the cpu (1.1 v). the problem is sending a signal from the low i/o voltage device to the high i/o device. with input
17 s1 switching from high to low and input s2 switching from low to high, output d1?s waveform is markedly different from d1?s output when s1 and s2 both switch from high to low. the waveform looks a lot better with sref (1.3 v) greater than the cpu i/o voltage (1.1 v), but because of process reliability issues the serf? voltage cannot be greater than the cpu supply voltage. answer: the gtl2000 is specified at 15.2 ma with the sref at 1.365 v with the dn at 0.175 v. when the sref is at 1.1 v, the on resistance of the channel is degraded. the observation being referred to is that if both channels make a high to low transition at the same time the fall time of the dn side is slower than if one is falling and the other is rising. there are 2 reasons for this observation: 1. first is that there is some capacitive coupling between the drain and the gate and between the source and the gate. when the channels have opposite transitions, the coupled charges cancel out. when they are in the same direction they perturb the voltage on the gref node making the channels weaker to pull the dn nodes down. role of the capacitor on the gref node is to minimi ze this effect, however because the gref pin has package inductance and the esd protec tion includes some series resistance, the decoupling capacitor benefit is limited. 2. second is that a sref at 1.1 v results in an effec tive lower gate overdrive voltage, so the on resistance is higher. the 300 k ? resistor to the 3.3 v supply biases the gref to just a threshold above the sref voltage. in the case of sref = 1.1 v rather than sref = 1.365 v the gref will be 0.265 v lower. possible techniques to improve the behavior: 1. include larger decoupling capacitor. this slows down the rc time constant of the gref node. 2. lower the value of the bias resistor so that it provid es more charging current for the gref node. it will also increase the leakage current at sn = sref. 3. decrease the sn low voltage to comp ensate for the high er on resistance. 4. operate the channel at a lower current by raising the high voltage side resistor. this trades high to low for low to high delay. 5. double up on channels (combine two i/os), this incr eases the capacitance at the level shifter because of the two channels and reduces the on resistance. 7. question: why did we use gref at 3.3v and inputs on that side at 2.5v for the timing test setup and why not 2.5v on gref and the inputs to 1.5v sref or 3.3v gref and inputs to 1.5v sref? answer: the vref or sref for the test circuit is 1.365 v to 1.635 v, with the gref and dref connected together and tied through a 200 k ? resistor to 3.3 v so the difference is 1.66 v which satisfies the 1.5 v requirement and the translation is 1.5 v (1.365 - 1.635) to 2.5 v. for the 2.5 to 3.3 v case, the resistor to gref should be to 4 v or higher if 3.3 v is used the low side high voltage will be degraded below the 2.5 v on the sref. applications 1. question: can i use the gtl2010 to level shift from 1.5 v to 3.3 v and from 1.5 v to 5 v at the same time? answer: yes, as long as the low side high voltage is the same for both translations, in this case 1.5 v. in this case, the sref can be connected to 1.5 v and different transistors used, i.e. source side on the 1.5 v level and the drain of one at 3.3 v and the drain of the other at 5.0 v as shown in figure 16. the pull up resistors would need to be sized so as not to exceed the maximu m allowed current (i.e., 15 ma) for the gtl-tvc device. 2. question: how does the gtl-tvc device act like a termination for the gtl line? answer: gtl and gtl+ logic families rely on incident wave switching which require the line to be terminated at the end with a resistor equal to the effective z 0 of the line to prevent reflections. the line in gtl /gtl+ systems is generally used point to point with one termination resistor but could be use on a bus with multiple drivers, so it is driven from the middle and termination is required at both ends. the gtl-tvc device can be used in place of the termination at an end by sizing the resistor on the high voltage side (dn side) to provide the same low state current that the termination resistor would have provided (i.e., gtl/gtl+ is about 15 ma). 3. question: i have worked with the intel 845 northbridge chip set and i?m trying to use th e gtl-tvc translators to interface a standard 3.3v pci chip to the 1.5 v agp bus of the i845. any in formation related to my application would be appreciated. answer: the intel reference design doesn't use the same re sistor values as we recommend. they use 1 k ? for the 1.5 v side and 2.2 k ? for the 3.3 v and 5 v side. gref and dref are connected together with a 200 k ? resistor.
18 use sref to clamp the sn port at 1.5 v so the 3.3 v dn port side signal is clamped at 1.5v without having to use any pull up resistors on the lower voltage side. when going from 1.5 v to 3.3 v a pull up resistor has to be used on the 3.3 v dn port side. the gtl-tvc devices don't have a direction pin that makes them very nice for bi- directional level translation. the timing budget in agp is quite tight so devices have to be as fast as possible. both agp and pci do not have a signal to control the direction of the data so devices that don't have a direction pin (e.g., gtl-tvc) are very convenient. regarding the pull-up on the pci side, in a typical pci environment, only the control signals need pull-ups and those are provided by the motherboard. the stability of the rest of the signals is guaranteed by parking the bus. in the case where the pci chip is not connected to the motherboard pci bus, pull-up resistors on the control signals are required. 4. question: both the pci 3.3 v and agp 1.5 v are push-pull logic and most of the signals are bi-directional. for me it's clear that going from agp 1.5 v to pci 3.3 v needs pull up resistors to pull the signals up, so i need pull-ups on the pci side. from the pci 3.3 v side to the agp 1.5 v we only need to clamp signals so my question is: can i save the pull-ups on the agp side? answer: yes, a pull-up is not required on the agp 1.5 v side unless there are reflection related noise problems. if this is a gtl application with incident wave switching wh ere typically both ends of the bus are terminated with the characteristic impedance of the bus, the gtl-tvc translator will replace one of the terminations. unless the agp edge rates are fast enough or the data rate is so high th at the line needs to be terminated at both ends, the gtl20xx translators can provide the pull-up using current from the 3.3 v side and no pull up resistors are needed on the 1.5 v side. 5. multi-part question : we want to use the philips gtl2010 for level shifting between intel gmch dvo @ 1.5 v and our tv encoder @ 3.3 v. the diagram shown in figure 17 is the reference circuit recommended by the tv encoder vendor. in the recommended circuit, there are two levels of voltage shifting, 1.5 v to 3.3 v and 1.5 v to 5 v. we will only use the level shifting of 1.5 v to 3.3 v by putting gref (pin 24) and dref (pin 23) to 3.3 v dd . the signal running through the gtl2010 is the open drain i 2 c bus, bi-directional for the i 2 c data and uni-directional for the i 2 c clock. question a: do you think that the circuit shown in figure 17 is well designed? do you have an advice for the design? answer a: you could try removing the pull up resistors on the 1.5 v side since the 3.3 v pull ups pass through the device and will pull the 1.5 v line high to the clamping voltage of 1.5 v. you can also leave them on since it will not hurt. question b: vsn (on-state) = 0.2 v max, vdn (on-state) = 0.4 v max. is this the input specification? answer b: vsn is describing an input condition, vdn is describi ng the corresponding output condition. that is if a low of 0.2 v is forced on the sn pin the corresponding dn will be 0.4 v or less (but not less than sn) for the pull-up currents within the data sheet. question c: if 0.5 v is applied to the sn, doesn?t the fet become on-state because vsn (on-state) is 0.2 v maximum? answer c: the data path is a large nmos transistor, where the gate is nominally biased to a threshold above the reference source. anytime that an sn pin is forced to a voltage below the sref the nmos transistor will be on. the lower the sn voltage the lower the on resistance. that is if the sref is at 1.5 v and the gref and dref are connected together and a current limiting resistor of 200 k ? connects between a 3.3 v supply and the gref/dref node. then, if an sn pin is pulled below 1.5 v the corres ponding dn will start to pull current. the closer to 0.0 v that the sn gets the more current the dn will pull, or, desc ribed as on-resistance, the lower the sn voltage the lower the on-resistance. note: the lower the sref voltage the high er the effective on-resista nce, because the effectiv e vgs - vt is less since the vg follows the sref voltage. question d: the on-state values are not dependant on vs-ref but on the current throu gh the device. i do not understand why on-state value is not dependant on vs-ref. could you tell me the reason in detail? i think that if vs- ref is up, then vg of the fet is up and then voltage diff erence between vg and vsn will become large, therefore the vsn maximum voltage is more than 0.2 v.
19 answer d: the voltage drop between sn and dn depends upon both current and the difference between vs-ref and the voltage at sn. for a specific selection of vs-ref and vsn, the voltage at dn depends on the current. if the voltage of the sref pin is raised, the necessary voltage on the sn pin will rise if the same current and voltage drop between sn and dn are considered. if the voltage at dn is consider ed fixed and the same current is needed, the sn can only move up slightly even if the sref is raised substantially. question e: when voltage of sn is more than vs-ref (v), the fet is high impedance and when voltage of sn is less than 0.2v, the fet is low impedance. is this correct? by the way, i would like to know the relationship between fet impedance versus voltage of sn (or dn) or fet impedance versus current through the fet. do you have any measurement data? answer e: yes, see figures 8 to 13. when sn = sref, the bias circuit sets the current to a few microamperes, thus off, and for any sn voltage abov e sref, the leakage decreases. question f: please see the dc specification of our product circ uit. could you tell me your opinion whether this circuit works correctly? if not, could you advise? answer f: the tv encoder's vol of 0.4 v @ 2.0 ma limits the resistor choices because the current on the tv encoder side must not exceed 2.0 ma. if the 2.0 ma is divided into equal contributions from both the 1.5 v and 3.3 v sides, a minimum value of 1.1 k ? on the 1.5 v side and a minimum value of 3 k ? on the 3.3 v side are needed. higher value resistors could be used at the expense of increasing the rc time constants. if the power supply ranges were 10 % (i.e., 3.3 v 0.3 v) then the minimum resistor value would be set by the high supply limits (3.3 k ? on the 3.6 v (max) and 1.2 k ? on the 1.65 v (max) side). 6. question: on the gtl2002 parts, if you have a uni-directional signal that is being driven by an or gate, can this net be put directly into the part on the ttl side, or do you have to have the inputs all open drain with pull-up resistors? i would expect this be all right since there is no way the microprocessor will drive this signal low and short a ground to a driven signal. answer: the only possible problem is if the or gate output drive is very strong (i.e. fast edge rates), it may be desirable to add a series termination resi stor to the output of the or gate to prevent ringing and an over voltage at the microprocessor caused by ringing. if the or gate does not have fast edge rates there should be no problems. the gtl2002 will prevent any static over voltage of the micropro cessor input but if the edge rate is too fast there may be some dynamic over voltage. configuration is as following: sref connected to the microprocessor power supply, dref connected to gref and to a high value resistor (200 k ? ) to a power supply at least 1.5 v above the microprocessor supply, and uni-directional down translation). 7. question: we need a translator to convert signals from 5v to 3.3v and vice-versa. but the drivers are not open- drain. in this case, can i use gtl2000? answer: if the drivers are not open drain, you system needs to integrate some flag between the driving devices so there is no conflict by having one device driving a high level while at the same time the other one is driving a low level. there needs to be a way to prevent bus contention otherwise the devices would be damaged. with that in mind, the gtl2000 can be used. 8. question: is the gtl2000/02/10 capable of supporting i 2 c voltage level shifting in the standard-speed mode (100kbits/s), fast-speed mode (400kbit/s) and/or high-speed mode (3.4mbits/s)? answer: the gtl bi-directional voltage level translators are essentially frequency independent. so they should work at all three speeds. however, in addition to some seri es resistance, it also adds some capacitance to the wire. this is not a problem for the standard mode or fast mode, although it needs to be added to the total line capacitance. for the high-speed mode, the extra ca pacitance is probably undesirable, but the translators will communicate the signal if the rest of the capacitance is small enough. note: during a low to high event in the high-speed mode, the master's current source pull up will not up translate through the gtl voltage level translators. that is if the master is on the low voltage side of the translator, the current source pull-up ( active pull-up) will only pull-up the low voltage side of the bus because on the high voltage side of the translator, the high speed current source pull-up will cut off just below the clamp voltage (sref), leaving only the normal pull up resistor on the high voltage side to complete the low to high transition (sref to vcc). 9. question: gtl20xx in agp applications. so fa r, the agp specification is version 2.0 and the signal is specified at 1.5v. in agp specification 3.0, the signal will migrate to a 0.8v swing and i think this will be a problem using the gtl20xx devices. why was the low limit of the gtl20xx set at 1v? could it be used at 0.8v?
20 answer:: the low voltage limit is not in the dc specifications but the bullet under "features" states level translation down to 1 v. the gtl20xx devices sref is not recommended below 1 v to insure a low on resistance. the problem with a sref voltage lower than 1v is that the gate overdrive, or the amount that the gate voltage is above the threshold, decreases as the sref voltage is lowere d. this means that the nmos transistor does not turn on as hard and so the on resistance increases. once you get below a certain gate overdrive, the on resistance increases rapidly. the part will still be func tional, but the on resistance will be higher. 10. question : we want to use the gtl2010 to translate signals from 1.5 v to 3.3 v so our settings will be v sref = 1.5v, v dref = 3.3v. but we use only 6-bits of the 10-bit gtl2010, so there are 4-bits unused. we plan to use these other 4-bits for signal translation from 3.3v to 5v. lo oking through the application note we know that if the v dref is changed to 5v, then the gtl2010 can support both 3.3v and 5v output mix on the d side. but is it suitable for v sref to be changed to 3.3v so that the input will support both a 1.5v and 3.3v input mix on the s side? figure 18. application diagram answer: to protect the 1.5 v parts the sref must stay at 1.5 v and you will have to rely on the 3.3 v pull-up on the s side and the 5 v pull-up on the d side to get the high levels since the path will be essentially cut off above 1.5 v. it is possible to mix the voltages as proposed but the sref must be 1.5 v and the resistors on both the 3.3 v and 5 v sides determine the highs with the low being passed through the gtl2010. 11. multi-part question: i have a design where i need to translate voltage levels. my design needs fix 3.3v levels on d side. voltage levels on s side vary from 1.8v to 5v. so i did the following: 1. sref to 1.8 v, gref+dref through r = 200 k ? to 5 v, d pins pull-ups to 3.3 v. this is 1.8 v compliant on s side. 2. sref to 3.3 v, gref+dref through r = 200 k ? to 5 v, d pins pull-ups to 3.3 v. this is 3.3 v compliant on s side. 3. sref+gref through r=200 k ? to 5 v, dref to 3.3 v, d pins pull-ups to 3.3 v. s pins pull-up to 5 v. i assume that dref pin is now vreference so it should not exceed 4.4v and should be 1.5 v below gref. this is 5.0 v compliant on s side. the level on d side is 3.3 v. question a: am i right for the last assumption and is my design correct? answer a: we assume that you are describing three diff erent parts or at least three different jumper configurations, that is the 1.8 v, 3.3 v, and 5 v are not all present on different sources and drains at the same time because the level shift can only be down to one low voltage level per part/configuration. the answer to 3 is yes, the s and d are labels, the elect rical characteristics are identi cal so connecting the sref and gref together and using a 200 k ? resistor to 5 v to bias them with the dref at 3.3 v is equivalent to connecting the dref and gref together and biasing them through the 200 k ohm resistor to 5 v, with the r r c1 0.1uf 5v 1.5v r r r 3.3v sign a u1 gtl2010 1 24 2 23 22 21 20 19 18 17 16 15 14 13 3 4 5 6 7 8 9 10 11 12 gnd gref sref dref d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 5v sign a 1.5v signal r r 3.3v signal r r r 3.3v 3.3v r r r r r 3.3v r r r r1 200k r r
21 sref at 3.3 v. the effect is that the maximum high level that will be passed by the clamp is slightly above 3.3 v, whether the 5 v signals are applied to sn or dn pins. question b: due to battery operation, we cannot afford to have 16ma pull-up current on 48 signals as this would result to current >700ma under certain conditions, so we opt for 3 to 4 ma per signal as a maximum. - how would that influence the speed? - what speed can i expect (in terms of rising/falling edges and frequency) and is the speed dependant on the value of pull-up resistors (higher resistors than recommended are used)? - is the speed influenced by r pull-up x c total or is the matter more complex? - i use a fpga that is 3.3v device with 5 v tolerant i/o? s. it has internal (active) pull-ups. can i rely on them (use them) when translating from 1.8v to 3.3v (up conversion) or from 5v to 3.3v (down conversion)? answer b: the speed, that is the rise time is directly the rc pr oduct, so higher resistors will result in a slower behavior. for bi-directional signal operation it is necessary to use passive pull-ups or have an external circuit prevent contention between a low on one side with a high on the other side. if signals are flowing in only one direction on some lines the active pull- up on those lines cannot result in a c ontention because only one side has a driver. if the signal is being driven from the higher voltage logic to the lower voltage logic input the active pull-up is all that is needed, however if the low voltage logic is the driver, it will be necessary to use a pull-up on the high voltage logic side in order for the high level to reach a full high. an open drain bus is the easiest way to handle bidirectional signals, however it requires passive pull-ups. a more exotic alternative to resistors is use of current sources because they give a faster rise for the same worst-case maximum current. 12. question: is it possible to have the gtl2000 with 2.5v and 3.3v on one side and 5v on the other side? answer: yes, if the 2.5 v and 3.3v low side voltages are present at different times / applications, the sref could be used to connect to the current low side voltage. if both 2.5 v and 3.3 v voltages are present at the same time on the low voltage side with 5.0 v on the high voltage side, the sref will need to be connected to the lowest voltage, 2.5 v in this case, and the voltage that will be passed on the 3.3 v pins would be 2.5 v. pull up resistors could be used on the 3.3 v pins to achieve 3.3 v. the unidirectional or bidirectional voltage can be applied on a per channel basis. the idea of bi-directional is that there are drivers on both sides of the gtl2000 that can be active, so the signal can flow in either direction. if the outputs are tote m pole outputs, some mechanism is required to prevent the contention of a high level on one side with a low level on the other. the use of open drain outputs eliminates the possibility of such a contentio n. uni-directional means only one side of each channel has a driver so contention is not possible. different channels in the same gtl2000 can be operated as bi-directional, uni-directional up translation or uni-directional down translation, and the high side voltages can differ, but the sref must be connected to the low side voltage in order to clamp to that voltage. 13. multi-part question: question a: i have been looking at using the gtl2000 for a 2.5-v fpga to 5-v sensor drive. here's my configuration: the fpga has to drive 17 control signals to a 5 v part. the 5 v part has 2 outputs that connect to the fpga. the fpga is not 5 v tolerant and cannot be configured to have open drain outputs. what configuration would be best for me to use? answer a: the clamp voltage would be set at 2.5 v and then each sn/dn pair can be used in a uni-directional (either direction) or bi-directional mode where you just need to treat each sn/dn pair individually. so the seventeen 2.5 v to 5 v signals would have no resistors on the 2.5 v side that are driven with the totem pole outputs and you would need to put pull up resistors on the 5 v side so the sensor input would see 5 v h (high) when the fpga is driving high or l (low) when the fpga is driving low. the 2 5 v to 2.5 v signals would not need the pull ups on the 5 v side if the sensor has totem pole outputs and you don't need pull up resistors on the 2.5 v side if you don't have too much leakage. question b: what if i was to up the fpga output voltage and input tolerance to 3.0 v or even 3.3 v? would the configuration be the same except for sref being pulled to 3.3 v instead of 2.5 v? answer b: yes, this is correct. 14. question: i want to use the gtl2010 as unidirectional conversion from 3.3 v to 1.5 v on some control signals to a cpu. i also want to have jumper override on these signals, so i want to put on the low side an option to either pull the signal up through a 2.2 k ? resistor or pull down through a 2.2 k ? resistor. if the high side is driving high and the low side is pulled down with the 2.2 k ? resistor, is it like having a 200 k ? resistor pulling up with a 2.2 k ? resistor pulling down (200 k ? connected between gref, dref to 3.3 v) thus getting a logical low on the low side? i cannot connect the low side directly to gnd or 1.5v.
22 answer: the jumper probably needs to disconnect the 3.3 v side. if the 3.3 v side driver is a push pull type driver it must be disconnected before the low side resistor jumpers ca n be effective. if it is open drain (nmos) then the pull down jumper would form a resistor divider with the pull up resistor (probably should still disconnect the 3.3 v side), if the pull-up resistor is a sufficiently high value it will look low. if the driver is strong it will pull the 2.2 k ? pull-up low through the gtl2010. please note that grounding sref will disconnect the 3.3 v side for all channels. i think that the bottom line is that the 3.3 v side needs to be disconnected in order for the 2.2 k ? jumpers to work because the on resistance of the gtl2010 is only a few ohms wh en either side is low and it only rises slowly as the low voltage rises until it is within less than 1 v below the sref then it rises like 1/(v applied - v of sref)**2 to about 200 k ? when v applied = v of sref and then increases exponentially. so the low could be pulled up by the 3.3 v side to above 0.75 v and a low on the 3.3 v side would certainly pull the 2.2 k ? pull-up resistor on the 1.5 v side low. 15. multi-part question: we intend to use the gtl2000 for a pci to agp converter. the device will bi-directionally translate 1.5 v to 3.3 v. question a: pull up resistors: we would like to be sure they are not needed on both sides of the device. our guess would be that they are needed only on the high side but they want to be sure. answer a: no pull-up is required on the low voltage side unless that side is known to have a significant leakage to ground i.e. >10 a. question b: propagation delay: spec says between 0.5 and 5.5 ns. they would like to have more info on that like simulations or characterization results if possible. answer b: the gtl2000 (and gtl2002 and 10) can be thought of as acting like a wire, with a little resistance and some capacitance. the characterization data that can be found in figure 19 shows the following: - the high to low transition is less than 1 ns with a strong pull-down driv er driving through the gtl2000. - the low to high transition is determined by the rc time constant. the ~1.2 ns in the characterization represents the added delay because of the capacitan ce of the gtl2000. the actual low to high transition time in the system is determined by the total rc time constant and the relevant pick off points. for example if the pull-up is 200 ? and the total capacitance is 100 pf, the time constant would be 20 ns and for a pick off point that is 1/2 the swing the delay would be ~14 ns. figure 19. propagation delay characterization results
23 16. multi-part question : we are using the gtl2000 for the one-way level shifting from 3.3v -> 1.8v. question a: let us know the set up time and the hold time of gtl2000. answer a: "set up and hold" are usually referring to flip flop or latch parts, so they have no meaning with respect to the gtl2000 parts. question b: when the transistor is off and the gref and dref are low, it is specified that the input and the output are don't care. when gtl2000 becomes this state, is this correct that all input and output of the gtl2000 become the high impedance. please let us know the maximum voltage we can induce to the i/o of gtl2000 when it is the high impedance. can we induce the 5.5v max to the i./o ? answer b: if the gref pin is at ground the transistors in the gtl2000 are off an d the path from each d to its s is high impedance. note : if the intent is to switch the gref pin the enable time and the disable time will depend upon how quickly the gref pin voltage transitions between ground and the bi as voltage for the appropriate level shift conditions. for example, let assume that the 200 k ? pull-up resistor is used to connect the gref and dref to the 3.3 v power supply and a 1 f capacitor is used for decoupling between the gref and dref node and ground. the rc time constant of the gref node would be 0.2 s meaning that the enable time would be on the order of 0.2 s. the disable time if the sref is connected to ground or if the gref is connected to ground by a transistor or open drain or open collector gate would be the delay of the gate because the internal time constant is only about 5 ns as soon as the gref falls below about 0.5 v the transistors are off. if the need is for the gtl2000 to enable and disable quickly about the best solution that could be recommended would be to use a high drive cmos gate (with a minimum high level drive current maximum of at least 15 ma), a series 50 ohm resistor between the cmos gate and the gref pin of the gtl2000 and a diode with its anode on the gref and 50 ohm resistor node and its anode to the 1.8 v power supply. this solution is fast ~ 10 ns at the expense of wasting about 15 ma of current and doing a less than perf ect translation. this will also require pull-up resistors on the low voltage side as well as the high voltage side because the diode forward does not match the threshold of the nmos transistors in the gtl2000. increasing the 50 ohm resistor if slow er enable and disable times can be tolerated can reduce power. additional information the latest datasheets for the gtl2000/02/10 bi-directional lo w voltage translators and other specialty logic products can be found at the philips semiconductors website: www.philipslogic.com additionnal technical support for gtl2000/02/10 bi-directiona l low voltage translator devices can be provided by e- mailing the question to: i2c.support@philips.com
philips semiconductors application note AN10145 bi-directional low voltage translators yyyy mmm dd 2 revision history rev date description _2 20040811 application note (9397 750 13933). supersedes data of 16 december 2002. _1 20021216 application note; initial version. definitions application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support e these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes in the productseincluding circuits, standard cells, and/or softwaree described or contained herein in order to improve design and/or performance. when the product is in full production (status `production') , relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2004 all rights reserved. printed in u.s.a. date of release: 08-04 document order number: 9397 750 13933

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